An integrated circuit (IC) is an interconnected network of microcircuits which form discrete IC devices. A microelectronic die comprises a die substrate upon which microcircuits are formed. The die substrates are diced from semiconductor material, examples of which include, among others, wafers of silicon (Si), gallium arsenide (GaAs), Indium Phosphate (InP) and their derivations. Various techniques are used, such as layering, masking, doping, and etching, to build thousands and even millions of microscopic IC devices in the form of transistors, resistors, and others on the wafer. The IC devices are interconnected within individual dice to define a specific electronic circuit that performs a specific function, such as the function of a microprocessor or a computer memory.
Optical micro-lithography is a process used to produce ultra-high resolution features on the wafer. One type of optical micro-lithographic system is known as step and scan. The step and scan system comprises three primary subsystems: a laser subsystem to provide the radiation source; beam focusing and scanning subsystem that shapes and guides the radiation; and a wafer subsystem in which the wafer is held and positioned at the focus of the radiation. Micro-lithography systems must overcome a multitude of challenges to produce an image that is suitable for resolving 65 nanometer features and below.
The challenges of providing error-free lithographic projection can be addressed at the subsystem level. The laser subsystem must provide, among other things, a radiation beam at a predefined wavelength and uniformity of power. Laser subsystem errors develop where the wavelength and/or power of the radiation drifts from nominal.
The beam focusing and scanning subsystem must process, focus and direct the radiation in order to illuminate predetermined areas of the wafer. This subsystem comprises lenses, filters, mirrors, and positioning mechanisms that can contribute to errors. Errors occur at the lenses due to issues of alignment, astigmatism, as well as compaction and absorption that can vary over time.
The wafer subsystem comprises a wafer stage that positions the wafer during scanning. At the wafer stage, errors are introduced due to wafer handling, including issues related to the wafer chuck flatness, alignment, conveyance, positioning, and control systems. The positioning mechanisms have issues related to mechanical devices, such as wear, inertia, and vibration. The control systems must provide suitable algorithms for numerical control of the positioning actuators, with feedback control for dynamic correction. At the reticle stage, the illumination is shaped by passing the radiation through an illumination slit or slot to illuminate the desired scan field.
Step and scan refers to the process in which the wafer is imaged. The reticle comprises a substrate with variable transmission properties that projects a rectangular exposure onto the wafer surface. The rectangular exposure is scanned across the surface of the wafer in multiple, predefined fields. The scanned field is also rectangular. Issues related to the quality of the illumination at the surface of the wafer are compounded by all the potential error issues of the individual subsystems, which can produce a scanned field that has issues of static and dynamic distortion, image plane deviations, and overlay.
Another important factor related to potential errors in the step and scan system include wafer quality. At the resolution level, wafer planarity is a crucial factor in image focus on a wafer surface. Control for real-time focusing is required to follow the terrain of the wafer. The focus is controlled by sampling a finite number of areas as the wafer is scanned. Servo controlled wafer stages adjust the position of the wafer to keep the wafer's surface at the optimum lithographic focal point.
Additional sources of focus error as a result of wafer quality include: vendor-specific wafer bevel and systematic non-parallelism; layer- and process-specific wafer thickness variation, such as interlayer dielectric (ILD) deposition and chemical and mechanical planarization (CMP) variations.
Focus error can also be caused by focus sensors and focus software interacting with machine variables. The errors of conventional metrologies and monitors of focus and tilt can also cause focus error, and in particular, where these errors are not the same during test and during production exposure.
These error issues accumulate at the exposure location, and therefore the errors must be tightly budgeted. In order to minimize errors characteristic in step and scan systems, the subsystems are held to the tightest of tolerance achievable, which dramatically increases the cost of the system. In-line monitoring is used but is limited by sampling rate and damage assessment/mitigation.
Because a wafer stage will be moved on a trajectory unique by the layer being patterned and product because of different stepping and sizing of fields, the control system needs to place the wafer stage in exactly in the correct position. In the absence of infinite forces available to do so, there will be deviations from that desired position in step and scan.
Methods are needed to control characteristic defocus inherent in the step and scan systems. As IC device resolution is made even smaller, negating these error issues becomes critical.